1. Field of the Invention
This invention relates to the field of virtualized computer systems.
2. Background Art
The advantages of virtual machine technology have become widely recognized. Among these advantages is the ability to run multiple virtual machines on a single host platform. This makes better use of the capacity of the hardware, while still ensuring that each user enjoys the features of a “complete,” isolated computer. Depending on how it is implemented, virtualization also provides greater security since it can isolate potentially unstable or unsafe software so that it cannot adversely affect the hardware state or system files. This and other advantages are also provided by virtualization even in systems with only a single virtual machine. Computer virtualization is described in greater detail below.
Proper virtualization of a computer architecture also requires virtualization of its mechanisms for servicing processor and interrupt priorities. For example, modern operating systems for use in systems compatible with Intel's IA-32 architecture (commonly referred to as “x86”) make extensive use of the fine-grain interrupt protection facilities of the Advanced Programmable Interrupt Controller (APIC). Whether an APIC delivers interrupts to the processor core or not is influenced by the processor, task, and interrupt priorities implemented within the APIC. Operating systems frequently change priority levels to dynamically protect the processor from interrupts of certain kinds in select critical regions. Correct virtualization therefore also entails virtualization of the APIC.
Interrupt handling in contemporary Intel x86-based computing systems depends on the Advanced Programmable Interrupt Controller Architecture. Systems that conform to the APIC architecture include the Intel Pentium 4, Xeon, P6, AMD Athlon and Opteron. The APIC architecture defines two kinds of basic functional units: the local APIC unit and the external I/O APIC unit.
The local APIC unit is a per-CPU unit that is implemented in the processor core in contemporary x86 processors. Older Intel 82489DX systems had a “discrete APIC implementation” off-chip. A discrete implementation supported a programming interface similar to the modern integrated local APICs and conformed to the APIC architecture. The local APIC unit receives interrupts from the processor's pins, from internal sources, from external sources via I/O APICs or other processors, and then forwards them to the processor core for servicing when appropriate.
A multi-processor (MP)-compliant system must also contain one or more I/O APIC units implemented as a part of the chipset. The primary function of an I/O APIC is to manage interrupts originated externally to the processor (device interrupts, chipset interrupts) and to relay them to the destination processor. The local and I/O APIC units communicate either through a dedicated APIC bus or a general system bus via APIC messages.
As is mentioned above, complete and correct virtualization of a computer requires proper virtualization of the APIC as well. Often, however, the cost of priority virtualization dominates the entire APIC virtualization overhead and represents a significant fraction of the total virtualization cost. What is needed is therefore an efficient virtualization of processor, task, and interrupt priorities in order to maintain high performance. This invention provides such a virtualization method and system.